The present invention relates to semiconductor memory devices, and more particularly to an embedded dynamic random access memory (EDRAM) cell that contains double-gated vertical metal oxide semiconductor field effect transistors (MOSFETs) and isolation regions such as shallow trench isolation (STI) regions that are self-aligned to the wordlines and bitlines. The inventive memory cell, which is scalable below a minimum feature size, F, of about 110 nm, substantially eliminates backgating due to an adjacent wordline as well as problems caused by a floating-well. The present invention also relates to a method of producing the above-mentioned memory cell.
As conventional vertical DRAM cells are scaled below a design groundrule of about 110 nm, encroachment of the buried-strap region upon the sidewall of the adjacent storage trench cuts-off the path holes flowing into and out of the portion of the P-well above the buried-strap region.
Simulation has demonstrated that floating-well effects limit the scalability of prior art vertical DRAM memory arrays to a minimum distance of about 90 nm between adjacent storage trenches. A number of dynamic leakage mechanisms limiting the scalability of conventional vertical DRAM memory cells have been identified and quantified. Included in the dynamic leakage mechanisms are: (1) Floating-well bitline disturb (FWBD), (2) Transient drain induced barrier lowering (TDIBL), and (3) Adjacent wordline induced punchthrough (AWIPT).
The onset of serious charge loss due to each mechanism occurs at approximately 90 nm end of process deep trench (DT) to deep trench (DT) spacing. Thus, scalability of conventional vertical DRAM memory cells beyond about 110 nm is expected to be limited by floating-well effects.
An illustration of a dominant floating-well dynamic leakage mechanism that limits scalability of prior art vertical DRAM memory arrays is shown in FIG. 1. Specifically, at a time indicated by point A of FIG. 1 and during a long period of about 5-100 ms of repeated writing of a xe2x80x9c1xe2x80x9d to other memory cells on the bitline, the P-well of an unselected cell storing a xe2x80x9c1xe2x80x9d may leak up towards bitline voltage (Vblh), as the exiting of holes is restricted by parasitic JFET. Leakage depends on the degree of well isolation caused by pinchoff from expansion of the storage node depletion region. In an extreme case, the buried-strap region may come in contact with the adjacent deep trench capacitor. Moreover, the hole current through the pinchoff region must keep up with the leakage to avoid a pseudo xe2x80x9cFloating-Body Effectxe2x80x9d.
Insofar as time interval B-C is concerned, the N+ bitline diffusion to P-well barrier is lowered by a downward swing of Vblh. Electrons emitted from the bitline diffusion region are collected by the storage node resulting in the formation of a parasitic bipolar transistor, QB, (PWint is a floating base) within the memory cell array.
For aggressively scaled vertical metal oxide semiconductor field effect transistors (MOSFETs) in prior art vertical DRAM memory cells, the depletion region from the storage node diffusion (i.e., buried-strap outdiffusion) encroaches upon the sidewall of the adjacent storage trench, which results in dynamic charge loss from the storage capacitor as the bitline of an unselected device is cycled. This charge loss mechanism is identical to that published in xe2x80x9cFloating-Body Concerns for SOI Dynamic Random Access Memory (DRAM)xe2x80x9d, Proceedings, 1996 IEEE International SOI Conference, Jack Mandelman, et al. pp. 1367-137, October 1996.
An illustration of the storage capacitor voltage vs. the voltage in the portion of the P-well isolated by the depletion region from the buried-strap outdiffusion, as the bitline is cycled, is shown in FIG. 2. When the bitline is held at Vblh, the isolation portion of the P-well leaks up towards the voltage of the adjacent diffusions. With subsequent cycling of the bitline between 0.0 and Vblh, the dynamic charge loss mechanism results in charge pumping which discharges the storage capacitor. Between data refresh, greater than 106 bitline cycles are possible, which is sufficient to discharge the storage capacitor.
Another problem with prior art DRAM cells is backgating which causes back side leakage that is gated by the adjacent wordline in the DRAM CELL. An illustration of the backside leakage problem is shown, for example, in FIG. 3.
In view of the drawbacks mentioned hereinabove with prior art memory cells (i.e., floating-well effects and backgating); there is a continued need for developing a new and improved memory cell which is substantially immune to the floating-well and backgating problems.
One object of the present invention is to provide a memory, cell that substantially eliminates floating-well effects that are typically present in prior art memory cells.
Another object of the present invention is to provide a memory cell that substantially eliminates the prior art backgating problem due to an adjacent wordline.
A further object of the present invention is to provide a memory cell that is scalable below a minimum feature size of about 110 nm.
These and other objects and advantages are obtained by providing a memory cell which includes at least double-gated vertical MOSFETs and isolation regions that are self-aligned to the wordlines and bitlines of the cell. The double-gated vertical array MOSFETs provide for stronger gate control, higher current drive, steeper sub-threshold, i.e., Vt, slope, reduced substrate sensitivity, reduced short channel effect (DIBL) and allows for larger deep trench, DT, width.
In one aspect of the present invention, a method of producing a memory cell which includes at least double-gated vertical MOSFETs and isolation regions that are self-aligned to the wordlines and bitlines of the cell is provided. The inventive method includes the steps of:
(a) forming a plurality of deep trenches in a Si-containing substrate in an array portion of a memory cell, said plurality of deep trenches being arranged in rows and columns and including at least collar filled divot regions which are filled with a strap placeholder material;
(b) forming double-gated vertical MOSFETs in said plurality of deep trenches, wherein said double-gated vertical MOSFETs include at least two gates on opposing sidewalls and exposed gate conductors, wherein one of said sidewalls also contains a buried-strap region;
(c) forming wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductors, wherein said wordlines are formed in said column direction;
(d) protecting said array portion of said memory cell;
(e) forming support MOSFETs while said array portion is protected;
(f) protecting said support MOSFETs;
(g) forming sidewalls spacers on said double-gated vertical MOSFETs;
(h) forming bitlines on said Si-containing substrate that are orthogonal to said wordlines; and
(i) forming isolation trench regions into said Si-containing substrate adjacent to said rows of deep trenches, wherein said isolation trench regions have a depth that is deeper than abutting bitline diffusion regions.
In one embodiment of the present invention, the buried-strap is confined to a location that is at a central portion of at least one sidewall of the MOSFETs.
It is noted that the inventive method described by processing steps (a)-(i) above is a dual workfunction and lithography friendly process. Moreover, the inventive method decouples the array and support process and eliminates an active area (AA) mask (critical mask) for the array process.
Another aspect of the present invention relates to a memory cell which includes at least double-gated vertical MOSFETs and isolation regions that are self-aligned to the wordlines and bitlines of the cell. Specifically, the inventive memory cell array comprises:
a plurality of memory cells formed in an array portion of a Si-containing substrate which are arranged in rows and columns, each memory cell including a double-gated vertical metal oxide semiconductor field effect transistor (MOSFET) having exposed gate conductor regions and two gates formed on opposing sidewalls of said MOSFETs, wherein one of the opposing sidewalls also includes a confined buried-strap;
a plurality of wordlines overlaying said double-gated vertical MOSFETs and in contact with said exposed gate conductor regions, said wordlines being arranged in said column direction;
a plurality of bitlines that are orthogonal to said wordlines; and trench isolation regions formed adjacent to said rows of memory cells, wherein said trench isolation regions have a depth that is deeper than abutting bitline diffusion regions.